1. Field of the Invention
The invention relates to a method for fabricating a capacitor in an integrated circuit (IC), and more particular to a method of reducing the leakage current in a dielectric material with a high dielectric constant by using three steps of annealing processes.
2. Description of the Related Art
In a DRAM, the typical method to access data is by charging or discharging optionally into each capacitor of the capacitor array on the semiconductor substrate.
Due to the higher and higher integration of IC, dimensions of devices or structures (such as transistors, capacitors) become smaller and smaller. Thus, the storage of charges (that is, the capacitance) of the capacitor in the design of a conventional planar capacitor decreases. The decrease of charge storage causes various problems, including mechanical deterioration and charge leakage by the larger susceptibility, and therefore, causes potential loss. The charge leakage caused by larger susceptibility may cause more frequent refresh period, and by which, memory can not handle data saving and reading properly. Moreover, the decrease of charge storage may need more complex data reading plan, or more sensitive charge induction amplifier.
Up to now, there are three ways to solve the problem of low capacitance of a capacitor resulted from the higher integration in a very large scaled integrated circuit. The first method is to reduce the thickness of the dielectric layer between two conductors of the capacitor. It is known that the capacitance is proportional to the inverse of distance between two conductors in a capacitor. Thus, the decrease of the thickness of dielectric layer increases the capacitance effectively. However, according to the consideration of the uniformity and stability of the dielectric layer, this is a method difficult to control. The second method is to increase the surface area of the storage node of the capacitor. The capacitance is proportional to the surface area of storage node, that is, the conductor (electrode). Therefore, to increase the surface area of the storage node increases the capacitance as well. The very common structure for increasing the surface area is the fin-shape, box-shape structure, or hemispherical grain structure. These kinds of structures are complex for fabrication, and thus, cause the difficulty in mass production. The third method, which is the most direct method, is to adapt the material with high dielectric constant, such as, tantalum oxide (Ta.sub.2 O.sub.5), as the dielectric layer. However, in the conventional process, the high leakage current and low breakdown voltage caused by the arrangement of tantalum oxide still needs to be improved.
In a conventional DRAM process, after deposition, a tantalum oxide layer formed on a substrate is in an amorphous state. An annealing process is performed to transform the amorphous tantalum oxide layer into a crystalline state. Referring to FIG. 1, a relation between temperature and annealing time for transforming the amorphous tantalum oxide layer into a crystalline tantalum oxide layer is shown. To performed a rapid thermal anneal, the substrate is put in an environment of nitrous oxygen (N.sub.2 O) at a temperature of about 800.degree. C. for about tens of seconds, for example, 60 seconds. The lattice of the tantalum oxide layer is re-arranged by absorbing thermal energy. That is, a step of nucleation and grain growth of the tantalum oxide layer is performed to obtain a more regular structure. However, though the tantalum oxide layer is re-nucleated and grown, due to the very short time of the annealing process, the obtained grain size of tantalum oxide layer is still too small. Therefore, the leakage current of tantalum oxide layer is still considerable.